1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, a synchronous semiconductor memory device.
2. Description of the Related Art
In general, a memory device such as a synchronous DRAM, for reading and writing data in synchronization with a clock signal utilizes burst read and write schemes. The burst read scheme is a high-speed data reading method where data corresponding to the number of bursts for a single enabled address is output in response to consecutive clock signals. More specifically, in the burst read scheme, a column selection signal for a column is enabled in response to a clock signal, and data is read. Next, the column signal is disabled in response to a next clock signal, and a next column selection signal is enabled. The data is read by repeating these operations.
The memory device utilizing the burst read and write schemes generally comprises pipelined circuits. During a read operation, each of the pipelined circuits stores data read from a plurality of memory cells and outputs the data to the exterior through an output driver in synchronization with a predetermined clock signal. In addition, during a write operation, each of the pipelined circuits stores a large amount of write data received from the exterior though an input driver, and transmits the data to the memory cells in synchronization with the clock signal.
The semiconductor memory device with the pipelined circuits can perform the read and write operations on a plurality of memory cells in one time. An example of the semiconductor memory device with the pipelined circuits is disclosed in U.S. Pat. No. 5,923,615.
On the other hand, as the input/output speed of the DRAM is getting higher, memory systems having a point-to-point bus architecture are widely used. However, it is difficult to connect a large number of devices to the memory systems having the point-to-point bus architecture. For example, in a memory system having a 64 bit bus width, if four memory devices having an input/output data width of ×16 are connected to the memory system, the 64 bit bus width is completely filled. Therefore, an additional memory device is no longer connected to the memory system.
In a conventional semiconductor memory device, an input/output data width is fixed. In other words, the conventional semiconductor memory device has a single specified input/output data width. For example, a memory device having an input/output data width of ×16 comprises 16 pipelined circuits. The memory device further comprises 16 output drivers and 16 input receivers which are connected to the 16 pipelined circuits. FIG. 1 illustrates a semiconductor memory device having an input/output data width of ×16.
Referring to FIG. 1, a semiconductor memory device 10 comprises a memory cell core 11, a pipelined circuit 12, an input/output circuit 13, and a control unit 14. The semiconductor memory device 10 simultaneously outputs or receives 16 bits of read/write data through 16 pads P1˜P16.
However, since its input/output data width is fixed, the conventional semiconductor memory device has a limitation in use for the aforementioned memory system which it is difficult for a large number of devices to connect, for example, a memory system having a point-to-point architecture.
In order to solve the problem, a semiconductor memory device having a fuse circuit used to change an input/output data width is proposed. The fuse circuit is connected between a pipelined circuit and a line for a control signal. The pipelined circuit is enabled in response to the control signal. After the fuse circuit is cut, the control signal cannot be received, and the corresponding pipelined circuit no longer operates. In the conventional memory device having such a fuse circuit, the input/output data width of the memory device can be changed only once.
For example, a semiconductor memory device having a maximum input/output data width of ×16 comprises 16 pipelined circuits, 16 output drivers and 16 input receivers connected thereto. When fuse circuits connected to eight of the 16 pipelined circuits are cut, the input/output data width of the semiconductor memory device changes into ×8. As a result, only the eight pipelined circuits connected to the remaining uncut fuses can operate.
In the conventional semiconductor memory device, since only specified pipelined circuits and their corresponding input/output circuits operate, there is a limitation of increasing data input/output speeds.
Accordingly, it would be desirable to provide a low power consumption semiconductor device capable of selectively changing an input/output data width, as needed, and selectively operating a pipelined circuit based on a set input/output data width.
It would also be desirable to provide a low power consumption semiconductor device capable of selectively operating an input/output circuit based on a set input/output data width.
It would further be desirable to provide a data input/output method in a semiconductor memory device capable of selectively changing an input/output data width, as needed, and selectively operating a pipelined circuit based on a set input/output data width.
It would still further be desirable to provide a data input/output method in a semiconductor memory device capable of selectively operating an input/output circuit based on a set input/output data width.
According to an aspect of the present invention, a synchronous semiconductor memory device comprises a memory cell core, data input/output circuit unit, a pipelined circuit unit, and a plurality of selection units. The memory cell core has a plurality of memory cells. The data input/output circuit unit sets an input/output data width in response to input/output control signals and inputs/outputs data signals through all or some of a plurality of input/output pads. The pipelined circuit unit is connected to the data input/output circuit unit through input/output lines and transmits the data signals between the memory cell core and the data input/output circuit unit in synchronization with a predetermined clock signals through an input/output path selected in response to pipeline enable signals. The plurality of selection units are connected to the input/output lines through external common data lines and connect some of the input/output lines to the data input/output circuit unit in response to selection control signals.
According to another aspect of the present invention, a memory device, comprises: a memory cell core adapted to store data; a plurality of input/output connections adapted to communicate the data to and from the memory device; a pipelined circuit unit adapted to communicate the data to/from the memory cell core in response to pipeline enable signals; and a plurality of selection units each adapted to selectively communicate the data between the pipelined circuit unit and selected ones of the plurality of input/output connections in response to selection control signals, wherein a number of the selected ones of the plurality of input/output connections equals an input/output data width of the memory device.
According to still another aspect of the present invention, a method of inputting/outputting data for a synchronous semiconductor memory device having a memory cell core, a plurality of pipelined circuits and a plurality of selection units, the method comprises (a) setting an input/output data width; (b) enabling at least some of a plurality of input/output circuits based on the set input/output data width; (c) when all of the input/output circuits are enabled, (i) enabling all pipelined circuits and disabling all selection units, and (ii) inputting/outputting data through the enabled pipelined circuits and input/output circuits; and (d) when less than all of the input/output circuits are enabled, (i) enabling at least one of a plurality of selection units having a number of output signals corresponding to the input/output data width, and disabling other selection units; (ii) enabling a same number of the pipelined circuits as enabled input/output circuits, based on a column address signal; and (iii) inputting/outputting data through the enabled pipelined circuits, the at least one enabled selection unit, and the enabled input/output circuits.